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作者:Arindam Banerjee , Samayita Sarkar , Mainuck Das and Aniruddha Ghosh
来源:[J].International Journal of Advanced Computer Research (IJACR), 2015, Vol.5 (18)ACCENTS
摘要:Energy efficient test-able binary logarithmic multiplier and divider architecture using reversible logic has been reported in this paper. The focus of this paper is to avoid multiplication and division stages to reduce large layout area and make the circuit efficiently test-able....

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