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作者:Chatterjee Basab , Biswas B
来源:[J].IETE Journal of Research(IF 0.2), 2010, Vol.56 (6), pp.346DOAJ
摘要:A classic phase lock loop (PLL) consists of a voltage controlled oscillator (VCO), a phase detector (PD) or phase comparator and a loop filter. The characteristics of a PLL are well established. A modification is introduced in the VCO in the name of phase modulation input along w...
作者:Chatterjee , Biswas
来源:[J].IETE Journal of Research(IF 0.2), 2010, Vol.56 (6), pp.346-351Taylor & Francis
摘要:Abstract(#br)A classic phase lock loop (PLL) consists of a voltage controlled oscillator (VCO), a phase detector (PD) or phase comparator and a loop filter. The characteristics of a PLL are well established. A modification is introduced in the VCO in the name of phase modulation ...
作者:Zhiyong Dai , Zhen Zhang , Yongheng Yang ...
来源:[J].International Journal of Electrical Power and Energy Systems(IF 3.432), 2020, Vol.116Elsevier
摘要:Abstract(#br)Harmonics in single-phase systems challenge the performance of quadrature signal generator-based phase-locked loops (QSG-PLLs). This paper proposes a Luenberger observer-based PLL (LO-PLL) to address the issue. The proposed method enhances the harmonic suppression ca...
作者:Yalcin Balcioglu , Gunhan Dundar
来源:[J].Integration, the VLSI Journal(IF 0.414), 2017, Vol.58, pp.142-154Elsevier
摘要:Abstract(#br)In this paper, we present a new approach that provides a complete design, analysis, and high-level synthesis (HLS) flow for all-digital phase locked loops (ADPLL). CellPLL uses a methodology for direct design of transfer functions given a set of specifications by the...
作者:T. M. Sathish Kumar , P. S. Periasamy
来源:[J].Wireless Personal Communications(IF 0.428), 2018, Vol.102 (4), pp.3343-3359Springer
摘要:Abstract(#br)Phase locked loops (PLLs) are utilized as a part of clock recovery and frequency synthesis. Entirely digital PLLs are more reasonable for the solid execution with different circuits contrasted with the customary usage of the PLLs. The all-digital PLLs are additio...
作者:Anu Tonk , Neelofer Afzal
来源:[J].Integration, the VLSI Journal(IF 0.414), 2017, Vol.59, pp.90-97Elsevier
摘要:Abstract(#br)This paper presents a symmetric review of academic and accomplished research endeavors in the field of Sub-Sampling Phase Locked Loop (SSPLL) design. Adequate emphasis has been given to understand the yearn for development of Sub-Sampling PLLs. Techniques that have e...
作者:Adesh Kumar , Gaurav Verma , Mukul Kumar Gupta
来源:[J].Wireless Personal Communications(IF 0.428), 2017, Vol.97 (1), pp.773-787Springer
摘要:... The design approach is based on digital components rather than analog components such as phase detector, loop filter and voltage controlled oscillator. The signal is presented using digital words instead of analog voltages. In digital FM receiver, PLL is the main part to capt...
作者:Kamayani Shrivastav , R. P. Yadav , K. C. Jain
来源:[J].Wireless Personal Communications(IF 0.428), 2019, Vol.109 (1), pp.563-577Springer
摘要:Abstract(#br)This paper addresses a statistically optimal joint maximum a posteriori (MAP) data detection and phase noise (PHN) estimation algorithm for iterative orthogonal frequency division multiplexing (OFDM) receivers, used for high speed and high spectral efficient wir...
作者:K. K. Abdul Majeed , Binsu J. Kailath
来源:[J].Analog Integrated Circuits and Signal Processing(IF 0.553), 2017, Vol.93 (1), pp.29-39Springer
摘要:This work has been focused on designing a phase locked loop (PLL) operating in the GHz range with reduced reference spur and power requirement suitable for wireless communication applications such as wireless receivers, serial link trans-receivers and military communication. A n...
作者:Basab Chatterjee , B Biswas
来源:[J].IETE Journal of Research(IF 0.2), 2010, Vol.56 (6), pp.346-351Wolters Kluwer
摘要:A classic phase lock loop (PLL) consists of a voltage controlled oscillator (VCO), a phase detector (PD) or phase comparator and a loop filter. The characteristics of a PLL are well established. A modification is introduced in the VCO in the name of phase modulation input along w...

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