全部文献期刊学位论文会议报纸专利标准年鉴图书|学者科研项目
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作者:Sunil K Moon1 Rajeshree D Raut2
来源:[J].ICTACT JOURNAL OF COMMUNICATION TECHNOLOGY, 2018, Vol.8 (4)ICT Academy of Tamil Nadu
摘要:Secret information concealing using steganography is simple but to maintain its security, perceptibility, robustness, embedding capacity and good recovery of both cover as well as secret information are the major issues. In this paper we have applied Block Plane Coding Technique ...
作者:Sunil K Moon1 Rajeshree D Raut2
来源:[J].ICTACT JOURNAL OF COMMUNICATION TECHNOLOGY, 2017, Vol.8 (4)ICT Academy of Tamil Nadu
摘要:Secret information concealing using steganography is simple but to maintain its security, perceptibility, robustness, embedding capacity and good recovery of both cover as well as secret information are the major issues. In this paper we have applied Block Plane Coding Technique ...
作者:尹帅
来源:[D].哈尔滨工业大学  2010CNKI
摘要:...4LSB)降低到(-0.4LSB, 0.2LSB),DNL从(-0.5LSB, 0.4LSB)降低到(-0.2LSB, 0.2LSB)。并对带有数字校正的系统进行动态参数仿真,得到其SFDR达到86dB,SNDR达到72dB。另外,使用SMIC 0.35μm混合信号CMOS工艺,设计流水线第一级电路,...
被引频次:-下载频次:110
作者:赵达勤
来源:[D].华南理工大学  2013CNKI
摘要:...4LSB/+0.4LSB,积分非线性INL为-0.3LSB/+0.6LSB;信噪失真比SNDR为61.3dB,有效位ENOB为9.9,功耗为7.0μW,FOM为73fJ/conv-step,到达了高能效ADC的水平。最终完成了版图的设计,核心版图面积为0.78×0.43mm2。
被引频次:-下载频次:-
作者:于奇
来源:[D].电子科技大学  2010CNKI
摘要:...4LSB,无杂散动态范围SFDR为82.4dB,总功耗530mW,满足CCD高清图像前端处理要求的性能指标,验证了前文的理论和电路级仿真。
被引频次:-下载频次:781
作者:Mudhafar M. Al-Jarrah , Zaid H. Al-Taie , Abdelrahman Abuarqoub
来源:[C].Future Networks and Distributed Systems2017ACM
摘要:... Embedding of data in the cover images was based on 2LSB and 4LSB spatial domain schemes. The feature vectors of clean images, 2LSB stego images and 4LSB stego images, 10,000 each, were analyzed. The detection accuracy results of the validation phase was 99.41% for the combine...
作者:孙彤
来源:[D].清华大学  2007CNKI
摘要:...5位,|DNL|小于2LSB,|INL|小于4LSB,功耗为1.2mW。
被引频次:10下载频次:723
作者:Shin Mhun , IKEBE Masayuki , MOTOHISA Junichi ...
来源:[J].ITE Technical Report, 2009, Vol.33.39, pp.75-80J-STAGE
摘要:...4LSB by simulation. In addition, utilizing deformation thermo-code, we reduced D-FFs of TDC. For 12bit A/D Converter, when the first stage 9bit ADC and the second stage 3bit TDC are considered, we can design the proposed ADC with only 13 of D-FFs. The linearity of A/D Conve...
作者:沈志远
来源:[D].东南大学  2006CNKI
摘要:...4LSB和0.2LSB,1GHz/s采样时功耗约为400mW。电路采用0.18微米CMOS工艺,电源电压1.8伏。
被引频次:5下载频次:637

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